The present invention relates to a technique for converting a data sequence of a transmission rate f1 to another data sequence of another transmission rate f2, and more particularly to a rate conversion apparatus for generating from clock signals of a frequency f1 to clock signals of another frequency f2.
The signal transmission rate is often converted in communication systems, and conversion is frequently accomplished from a signal transmission rate of f1 (samples/sec) into another transmission rate f2 which is equal to n/m times (m and n are mutually prime natural numbers) f1.
In one of the cases well known to persons skilled in the art where such processing takes place, data received over a line having a transmission rate f1 are sent out over another line having a transmission rate f2, which is not equal to f1. In another instance, data of an f1 transmission rate are subjected to error detection coding or error correcting coding to be converted into data of f2 in transmission rate (f1&lt;f2 in this case).
What is needed here is a generation of other clock signals of another frequency f2 from a clock signal of a frequency f1. For this purpose, a frequency synthesizer using a phase-locked loop (PLL) is often used. For details on such a frequency synthesizer using a PLL, reference may be made to F. M. Gardner, Phaselock Techniques (1979, John Willey & Sons, Inc.), pp. 208-214.
In the presence of a relationship of nf1=mf2 (where m and n are mutually prime integers) between the frequencies f1 and f2, this frequency synthesizer is composed of an m frequency divider for frequency-dividing signals of the frequency f1 by m and a PLL to which the output of the m frequency divider is supplied. The PLL further consists of a phase comparator having a first input terminals which is supplied with the output of the m frequency divider, a loop filter for filtering the output of the phase comparator, a voltage-controlled oscillator (VCO) having an oscillation frequency which varies around a center frequency of f2 according to the output of the loop filter, and the n frequency divider for frequency-dividing the output of the VCO by n and supplying the n frequency-divided output to a second terminal of the phase comparator. According to the prior art, clock signals of the frequency f1 are converted into clock signals of the frequency f2 in this manner. In this case, the frequency .DELTA.f of the signals entered into the two inputs of the phase comparator is equal to f1/m=f2/n. This method will be hereinafter referred to as the first method.
Incidentally, m and n sometimes may be very large numbers. If, for instance, f1 is 1.544 MHz and f2, 2.048 MHz, m will be 193 and n, 256, and in this case the frequency .alpha.f of the input signals of the phase comparator in the PLL would be equal to f1/m=f2/n=8 kHz. The bandwidth of the loop filter should be sufficiently narrower than 8 kHz, for example, around 1 kHz. The pull-in time of the PLL in this instance will be about 1 msec, which is an undesirably long pull-in time.
A conceivable solution to this problem, according to the prior art, is to replace the n frequency divider with an m times multiplier and the m frequency divider in the PLL with an n times multiplier. In this way, the frequency f0 of the two signals may be compared by the phase comparator equal to nfl=mf2. By this method (which will be hereinafter referred to as the second method), the input frequency f0 of the phase comparator is higher than f1 and f2, so that the bandwidth of the loop filter can be broadened and the pull-in time reduced. This method, however, entails a very high input frequency f0=nf1=mf2=395.264 MHz for the phase comparator, and the circuitry would be difficult to realize.